`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:32:52 04/05/2011 
// Design Name: 
// Module Name:    EXtoMEM_Buffer 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module EXtoMEM_Buffer(clk, mtIn, writeDstIn, RegWriteIn, MemtoRegIn, BranchIn, MemReadIn, MemWriteIn,
							ALUresultIn, zeroIn, signIn, branchAddrIn, ALUresultOut, zeroOut, signOut, branchAddrOut,
							mtOut, writeDstOut, RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut);

	input clk;
	input [15:0] mtIn;
	input [3:0] writeDstIn;
	input RegWriteIn, MemtoRegIn, BranchIn, MemReadIn, MemWriteIn;
	
	input [15:0] ALUresultIn;
	input zeroIn;
	input signIn;
	input [15:0] branchAddrIn;
	
	output [15:0] mtOut;
	output [3:0] writeDstOut;
	output RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut;
	
	output [15:0] ALUresultOut;
	output zeroOut;
	output signOut;
	output [15:0] branchAddrOut;
	
	reg [15:0] mtOut;
	reg [3:0] writeDstOut;
	reg RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut;
	
	reg [15:0] ALUresultOut;
	reg zeroOut;
	reg signOut;
	reg [15:0] branchAddrOut;
	
	always @ (posedge clk)
	begin
		mtOut <= mtIn;
		writeDstOut <= writeDstIn;
		RegWriteOut <= RegWriteIn;
		MemtoRegOut <= MemtoRegIn;
		BranchOut <= BranchIn;
		MemReadOut <= MemReadIn;
		MemWriteOut <= MemWriteIn;
		ALUresultOut <= ALUresultIn;
		zeroOut <= zeroIn;
		signOut <= signIn;
		branchAddrOut <= branchAddrIn;
	end
endmodule
